1. Field of the Invention
The present invention relates to a plating apparatus, a plating method and a multilayer printed circuit board.
2. Discussion of the Background
Japanese Unexamined Patent Application Publication No. 9-130050 discloses build-up multilayer printed circuit boards including filled vias. The contents of this application are incorporated herein by reference in their entirety.
Japanese Unexamined Patent Application Publication No. 2002-47594 (hereinafter referred as “the '594 publication”) discloses a method for manufacturing a multilayer printed circuit board having via holes which connect conductor layers provided on opposite sides of an insulation layer. The '594 publication further discloses that the upper surface of the via hole and the upper surface of the conductive circuit are formed on the same plane by using an electrolytic solution containing 50 to 300 g/l of copper sulfate, 30 to 200 g/l of sulfuric acid, 25 to 90 mg/l of chlorine ion, and 1 to 1,000 mg/l of an additive composed of at least a leveling agent and a brightener. The contents of this application are incorporated herein by reference in their entirety.